Guide Test Resource Partitioning for System-on-a-Chip

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The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements. Skip to main content Skip to table of contents. Advertisement Hide. Test Resource Partitioning for System-on-a-Chip.

dblp: Anshuman Chandra

Front Matter Pages i-xii. Front Matter Pages Test Resource Partitioning.

Access provided by: anon Sign Out. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length FDR codes Abstract: Test data compression and test resource partitioning TRP are necessary to reduce the volume of test data for system-on-a-chip designs. We present a new class of variable-to-variable-length compression codes that are designed using distributions of the runs of 0s in typical test sequences.

Read Now Test Resource Partitioning for System-on-a-Chip (Frontiers in Electronic Testing)

We refer to these as frequency-directed run-length FDR codes. We derive upper and lower bounds on the compression expected for some generic parameters of the test sequences. These bounds are especially tight when the number of runs is small, thereby showing that FDR codes are robust, i. At what levels: wafer test, initial package test, or burn-in and final test?

Each option must be evaluated and the test strategy and test-resource partitioning adjusted to achieve the highest test quality at the lowest cost. That typically means creating a matrix of the available test levels and the expected fault categories and figuring out what can best be tested where. This gets even more complicated when the design team has used the core assembly approach instead of the full chip synthesis approach.

The options offered with the full chip synthesis approach simply are not available using the core assembly approach, so DFT and test-engineering professionals need even more interaction with design teams and IP suppliers to get things right as quickly as possible. They must consider scan-chain type differences such as level-sensitive scan design LSSD vs.

DFT Strategies for SOC Designs

Test-strategy development and test-resource partitioning in this environment are much bigger tasks and have to be attacked much earlier in the process. Each IP element has to contain the necessary testability features, and those features must be reusable at the SOC level. Implementing some of the testing resources in the SOC design itself involves still another complex set of trade-offs. Some DFT and BIST implementations could have a negative impact on product performance if they interfere with critical, high-speed signal paths.

On the other hand, this extra time up-front can significantly reduce the test-program development time later on, actually shortening the overall time-to-market cycle. Also, there are issues associated with die size, wafer yield, and device packaging.

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Adding gates, flip-flops, or BIST structures can increase die size, reducing the total number of devices per wafer that can be fabricated. Bigger die sometimes can lower yield per wafer. They do, however, have to be considered in the context of tester cost, test development time, and device fault coverage in calculating the overall manufacturing and test costs for new designs.

Another element to be considered when developing DFT strategies for SOC designs is the cost of the tester and the use of that tester during the manufacturing process. Three principal factors drive the capital equipment cost for new ATE:.

Equivalence Partitioning In Software Testing - Test Design Technique

These effects tend to add to the basic tester functions required for things like continuity and DC parametric testing, handler binning, and overall test-program flow. Too much DFT and BIST may make a design too big to fit in the target package or too expensive in terms of silicon area, particularly in high-volume consumer applications. As a result, trade-offs must be made early in the device architecture development and detailed design phases to arrive at the right strategy.

In addition to the tester costs, the team is faced with adding expensive analog instrumentation to the ATE and executing tests that can be very time-consuming on the manufacturing test floor. Consider a design that includes multiple ADCs and DACs, and you can see how the test cost can easily begin to exceed the device fabrication cost.

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Fortunately, analog and mixed-signal BIST techniques now are available to help solve both the ATE cost and manufacturing test time problems. This technique also provides the test results in digital format via the IEEE Many organizations are looking for a silver-bullet, one-size-fits-all test strategy. That solution seldom exists because each design is unique.